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2.7
Dynamic Electrical Characteristics - Supply and SPI
V L ≤ (V CC - V SS ) ≤ V H , T L ≤ T A ≤ T H , | Δ T A | < 25 K/min unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
144
145
146
Power-On Recovery Time (VCC = VCCMIN to first SPI access)
Power-On Recovery Time (Internal POR to first SPI access)
SPI Reset Activation Time (CS high to Reset)
t OP
t OP
t SPI_RESET
—
—
—
—
—
—
10
840
300
ms
μ s
ns
(3)
(3,7)
(7)
147
148
Internal Oscillator Frequency
Test Frequency - Divided from Internal Oscillator
*
f OSC
f OSCTST
7.6
0.95
8
1
8.4
1.05
MHz
MHz
(7)
(1)
Serial Interface Timing (See Figure 7 , C MISO ≤ 80pF, R MISO ≥ 10kW)
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
Clock (SCLK) period (10% of V CC to 10% of V CC )
Clock (SCLK) high time (90% of V CC to 90% of V CC )
Clock (SCLK) low time (10% of V CC to 10% of V CC )
Clock (SCLK) rise time (10% of V CC to 90% of V CC )
Clock (SCLK) fall time (90% of V CC to 10% of V CC )
CS asserted to SCLK high (CS = 10% of V CC to SCLK = 10% of V CC )
CS asserted to MISO valid (CS = 10% of V CC to MISO = 10/90% of V CC )
Data setup time (MOSI = 10/90% of V CC to SCLK = 10% of V CC )
MOSI Data hold time (SCLK = 90% of V CC to MOSI = 10/90% of V CC )
MISO Data hold time (SCLK = 90% of V CC to MISO = 10/90% of V CC )
SCLK low to data valid (SCLK = 10% of V CC to MISO = 10/90% of V CC )
SCLK low to CS high (SCLK = 10% of V CC to CS = 90% of V CC )
CS high to MISO disable (CS = 90% of V CC to MISO = Hi Z)
CS high to CS low (CS = 90% of V CC to CS = 90% of V CC )
SCLK low to CS low (SCLK = 10% of V CC to CS = 90% of V CC )
CS high to SCLK high (CS = 90% of V CC to SCLK = 90% of V CC )
*
*
*
*
*
*
*
*
*
*
*
t SCLK
t SCLKH
t SCLKL
t SCLKR
t SCLKF
t LEAD
t ACCESS
t SETUP
t HOLD_IN
t HOLD_OUT
t VALID
t LAG
t DISABLE
t CSN
t CLKCS
t CSCLK
120
40
40
—
—
60
—
20
10
0
—
60
—
526
50
50
—
—
—
15
15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
40
28
—
60
—
—
—
35
—
60
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3)
(3)
(3)
(19)
(19)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(19)
1. Parameters tested 100% at final test.
2. Parameters tested 100% at wafer probe.
3. Parameters verified by characterization
4. (*) Indicates a critical characteristic.
5. Verified by qualification testing.
6. Parameters verified by pass/fail testing in production.
7. Functionality verified 100% via scan. Timing characteristic is directly determined by internal oscillator frequency.
8. N/A
9. Devices are trimmed at 100 Hz with 1000 Hz low-pass filter option selected. Response is corrected to 0 Hz response.
10.Low-pass filter cutoff frequencies shown are -3 dB referenced to 0 Hz response.
11.Power supply ripple at frequencies greater than 900 kHz should be minimized to the greatest extent possible.
12.Time from falling edge of CS to ARM_X, ARM_Y output valid
13.N/A
14.Thermal resistance between the die junction and the exposed pad; cold plate is attached to the exposed pad.
15.Device characterized at all values of V L & V H . Production test is conducted at all typical voltages (V TYP ) unless otherwise noted.
16.Data Path Latency is the signal latency from g-cell to SPI output disregarding filter group delays.
17.Filter characteristics are specified independently, and do not include g-cell frequency response.
18.Electrostatic Deflection Test completed during wafer probe.
19.Verified by Simulation.
20.Acceleration Data Request timing constraint only applies for proper operation of the Arming Function
MMA65xx
Sensor
10
Freescale Semiconductor, Inc.
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